DisplayPort 1.4 and Type-C Compliance/Debug Solution Datasheet
ثبت نشده
چکیده
DisplayPort 1.4 and Type-C Compliance/Debug solution key features Complete automated compliance testing in less than 7 hours for data rates up to HBR2 and less than 11 hours for data rates up to HBR3 Intelligent pattern recognition before test execution Fixture de-embed feature → Use the default filter file for de-embedding fixture effect or create a custom filter file using SDLA software to leverage the channel modeling and receiver equalization functionality Easy option to support repeatability of measurements Customization of reports according to Tests, Lanes, Data Rates or Pass/Fail results Timer pop-ups for zero user interaction during entire DisplayPort testing Enhanced TekExpress report with new measurement plots Single application for Standard and Type-C DisplayPort testing 100% DisplayPort High Speed transmitter test coverage Complete DUT automation for hands free testing Simplistic User Experience with single UI for DUT configuration Optimized algorithms execute tests with improved accuracy Optional signal validation helps to detect anomalies quickly in the signal Reports available in mht, pdf and csv formats for advanced data analysis Compliance (TekExpress) and Characterization (DPOJET) test support Support for DUT automation over SCPI based Programmatic Interface (PI) Automation support and scripting interface with Iron Python which supports socket based programming remote interface Supports Manual and Automated test modes for Type-C and Standard DP testing Stand-alone utility support for DPR-100 aux controller Capture and save DUT waveforms for offline analysis
منابع مشابه
A Spread Spectrum Clock Generator for DisplayPort 1.2 with a Hershey-Kiss Modulation Profile
This paper describes a spread spectrum clock generator (SSCG) circuit for DisplayPort 1.2 standard. A Hershey-Kiss modulation profile is generated by dual sigma-delta modulators. The structure generates various modulation slopes to shape a non-linear modulation profile. The proposed SSCG for DisplayPort 1.2 generates clock signals with 5000 ppm down spreading with a Hershey-Kiss modulation prof...
متن کاملA 2.7Gbps & 1.62Gbps dual-mode clock and data recovery for DisplayPort in 0.18μm CMOS
This paper describes a clock and data recovery (CDR) circuit that supports dual data rates of 2.7Gbps and 1.62Gbps for DisplayPort standard. The proposed CDR has a dual mode voltage-controlled oscillator (VCO) that changes the operating frequency with a “Mode” switch control. The chip has been implemented using 0.18μm CMOS process. Measured results show the circuit exhibits peak-to-peak jitters...
متن کاملA 1.62/2.7/5.4 Gbps Clock and Data Recovery Circuit for DisplayPort 1.2 with a single VCO
In this paper, a clock and data recovery (CDR) circuit that supports triple data rates of 1.62, 2.7, and 5.4 Gbps for DisplayPort 1.2 standard is described. The proposed CDR circuit covers three different operating frequencies with a single VCO switching the operating frequency by the 3-bit digital code. The prototype chip has been designed and verified using a 65 nm CMOS technology. The recove...
متن کاملAdaptive Equalizer for DisplayPort 1 . 1 a Standard
An adaptive equalizer is implemented for display port 1.1a standard with 0.13μm CMOS technology. Overall frequency response of the channel is flattened using high pass filter with current combiner. The adaptation block controls the amount of compensation by comparing the portion between high-frequency and low-frequency components. The fabricated chip consumes 11mW of power from 1.2V supply volt...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
عنوان ژورنال:
دوره شماره
صفحات -
تاریخ انتشار 2017